Research Projects:

  • Institute funded:
    • Machine Learning based Physical Design Automation for Next Generation ICs (2020 - )
    • Algorithms for Design Automation in Next Generation Technologies (2017 - 2020)
    • Logic Synthesis for Quantum Computing (2014 - 2017)
    • Physical Design of Three-dimensional ICs (2011 - 2014)
    • Techniques for Robust Physical Design on nanometer ICs (2008-2011)
    • Power Aware Placement (2006- 2008)
    • Parallel Algorithms related to Fragment Assembly in DNA Sequencing (2004-2007): Principal Investigator
    • Mulit-layer VLSI Routing (2002-2005)
    • Floorplanning in Deep Submicron Integrated Circuits (2001-2003)

  • Externally funded:
    • An efficient framework for ensuring security of FPGA-based application cores in Cloud and IoT environment (2019 - 2022); funded by SERB DST
    • Lithography aware physical design automation for below 20nm process technology, India-Taiwan S&T Cooperation programme, Global Innovation & Technology Alliance (GITA).
    • Parallel Implementation of H.264 CODEC" (2010-11); funded by Texas Instruments India Pvt. Ltd.
    • RET-aware Global Routing" (2010- ); funded by IBM Corp., USA.
    • Delay Fault Modeling and Test Generation for Power Supply Noise; (2003-2006), funded by Intel Corp., U.S.A.: Principal Investigator
    • CA-based BIST for asynchronous sequential circuits with B.E. College, Howrah; (1998-2001) funded by Strategic CAD Laboratories, Intel Corp., U.S.A.: Co-Investigator
    • CORCoP: Compilation and Optimization of Reconfigurable Co-Processors with IRISA Rennes, France; (1999-2002) funded by Indo-French Centre for the Promotion of Advanced Research: Joint Collaborator.